The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to a semiconductor device having a capacitor of large capacitance formed on a semiconductor substrate, and a method for manufacturing the same.
A dynamic random access memory (DRAM) in which a memory cell has a single MOS transistor and a signal MOS capacitor, can be given as one example of a memory device formed on a semiconductor substrate. In such a DRAM, the storage of information is carried out by storing a charge in a MOS capacitor. Also, the stored information is read out by discharging the MOS capacitor onto a bit line through an MOS transistor, thereby detecting the potential variances.
Recently, considerable progress has been achieved in the miniaturization and high packing density of DRAMs, along with the advance in semiconductor technology. The main concern for achieving high packing density in a DRAM is how to manufacture a capacitor with a large capacitance while minimizing the memory cell area.
It is well known that the capacitance of a capacitor is in direct proportion to the dielectric constant and the surface area of a dielectric film, and in inverse proportion to the thickness of the dielectric film.
Accordingly, in order to increase the capacitance, it is required to make the dielectric film thinner, to use an insulating layer of greater dielectric constant, or to enlarge the surface area of the dielectric film. However, thinning the insulating layer to increase the capacitance of the capacitor is undesirable since this would decrease the reliability of the semiconductor device. Although a method has been suggested which utilizes an insulating layer having a high dielectric constant such as tantalium oxide (Ta.sub.2 O.sub.5) film as the dielectric film, this method has not yet become practical.
Therefore, the enlargement of the capacitor's area is the preferable method to increase the capacitance of the capacitor. Vigorous researches to increase the effective area of a capacitor have been carried out, and various methods are proposed. For example, a method for forming capacitor having a storage electrode in a trench formed by etching a semiconductor substrate, or for forming a capacitor having a stacked-capacitor structure is employed.
Recently, a proposal in which the capacitance can be increased without enlarging the cell area or heightening the storage electrode, has been presented and has drawn a great deal attention. In published research literature ("Extended Abstracts of the 22nd on Solid State Device and Materials," 1990, pages 869 to 872 written by Yoshio Hayashide et. al., and pages 873 to 876 by H. Watanabe et. al.) there is disclosed a technique providing a polycrystalline silicon layer having an uneven surface as a storage electrode to enlarge the storage electrode's surface area due to its unevenness.
FIG. 1 illustrates a sectional view of a stacked capacitor having such an uneven surface. According to the method of Watanabe et. al., first, a field oxide layer 2 is grown on a silicon substrate 1 by a LOCOS method. A first polycrystalline silicon layer doped with an impurity is then formed as a gate electrode 3, followed a source region 4 and a drain region 5 being formed by ion implantation. Then, an oxide layer 6 is formed as an insulating layer. Thereafter, to form a storage electrode 7 serving as a first electrode of a capacitor, polycrystalline silicon is deposited by a low pressure chemical vapor deposition (LPCVD) at a temperature of 550.degree. C., thereby forming a first polycrystalline silicon layer. The specific temperature 550.degree. C. corresponds to the transition temperature of the structure at which silicon is transited from amorphous to polycrystalline. The surface area of the polycrystalline silicon layer deposited at the above-mentioned temperature is twice as large as that deposited at some other temperature.
A photoresist (not shown) is coated on the first polycrystalline silicon layer, and is exposed and developed through a mask, thereby forming a photoresist pattern. After that, storage electrode 7 is formed by etching the first polycrystalline silicon layer using the photoresist pattern as an etching mask, and then the photoresist pattern is removed. Successively, the oxide/nitride layer as a dielectric film 8 is formed on storage electrode 7, and a plate electrode 9 as a second electrode of the capacitor is formed by depositing a polycrystalline silicon on dielectric film 8 to form a second polycrystalline layer.
According to the above-described method, the polysilicon layer is applied to the storage electrode of a stacked capacitor structure, which enables the capacitance to be doubled. Further, Yoshio Hayashide et. al. teach the increase of capacitance by 1.5 times when the storage electrode is formed by depositing the polysilicon at 575.degree. C., relative to that of a conventional polysilicon storage electrode.
However, in manufacturing a capacitor according to the above-stated method, the temperature needs to be precisely controlled during depositing the polysilicon. Also, the thickness of the polycrystalline silicon layer constituting the storage electrode of the capacitor is an important factor for controlling the unevenness of the surface thereof, which in turn causes difficulty in manufacturing a capacitor having various structures. Additionally, since the patterning is performed by a photolithography and etching process after depositing, the surface of the etched sidewall becomes even, thereby decreasing the effect.
Therefore, to accomplish the present invention, the inventors of this application have studied the foregoing examples to solve the above-mentioned problems